1. Field of the Invention
The present invention is related to digital processing systems, more specifically, concerning identifying data coherency requirement and data caching requirement, with a piece of data residing in one or more different storage elements in a digital data processing system, providing access control code of a piece of data which relates more particularly to digital data processing systems with multiprogramming, and a mixed static and dynamic branch prediction method with correct static branch predictions on both in-loop (during looping) and loop-exit (exit from loops) branch predictions.
2. Description of the Prior Art
A digital data processing system (computer) instruction is composed of an opcode and one or more operands. The operands are data in either registers or memory. There are no qualifiers that explicitly specify the nature and system attributes for the data except those implied by the opcode. In a descriptor architecture computer, the operands in an instruction are specified by descriptors. A descriptor of an operand usually consists of a virtual address of the memory space of the operand, its data type and size, and vector specification if so exists.
To optimize the memory reference performance, operating systems specify if a page of data should be encached or not, so that unnecessary and undesirable data encaching will be avoided. It is also desirable to be able to specify if maintaining data coherency in a multiprocessing system is required. Such maintenance demands exhaustive checking, which creates performance bottlenecks and system complexity, but only a small percentage of data requires absolute data coherency. To provide protection to data, access code is often utilized to limit read, write and sometimes execution accesses to authorized and privile,ed processes.
At present, to specify a piece of data in a digital data processing system the system attributes such as encaching or maintaining data coherency, and access control of the piece of data, is on page basis through Translation Lookaside Buffer (TLB) via page table entries in page tables managed by memory management of operating systems. The data coherency is normally assumed to be required in a computer system. The access control on data is normally on per page basis and is implemented in the Translation Lookaside Buffer (TLB) via page tables managed by memory management of operating systems.
At present, in descriptor architecture computers, just like in others, system attributes such as access control on data, caching options to specify if a page of data should be encached or not, and ability to specify if maintaining absolute data coherency in a multiprocessing system is required, are on per page basis and not on individual operands.
The present computers contain branch prediction logic to predict with high accuracy if branching will take place for a conditional branch instruction or not. It is done so with static and dynamic branch prediction schemes. Static methods are based on compilers to generate object codes to identify to the processor if branching is likely or unlikely to occur. Dynantic methods are based on hardware to store histogram of earlier branching and not branching actions, and make an educated guess that branching will be talcen or not, for the current conditional branch instruction.
The present invention is an improvement over certain previous computer systems. An instruction consists of an opcode, and indexes of operand descriptors pointing to operand descriptors as a descriptor computer, and a branch prediction scheme.